From: Rainer Buchty (buchty_at_cs.tum.edu)
Date: 2004-05-03 23:22:04
> The 6522/6526 timers are counters which count PHI2 pulses. I need to
> count my own, "custom" pulses. Possibly, I could feed PHI2 with the
> clock I need to count, but I'm not sure.
>
> If the counter should count up or down depends on the status of another
> input line. The is, whenever a clock pulse comes in, the states of the
> other line determines if this clock pulse is meant to increment or
> decrement the counter. I need the absolute value afterwards.
-- snip --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity counter is
port(
clk, rst, dir, ena: in std_logic;
count: out std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of counter is
signal cnt: std_logic_vector(15 downto 0);
begin
process(clk,rst,dir)
begin
if rst='0' then
cnt<=(others=>'0');
elsif clk'event and clk='1' then
if dir='0' then
cnt<=cnt+1;
else
cnt<=cnt-1;
end if;
end if;
end process;
count<=cnt when ena='0' else (others=>'Z');
end architecture;
-- snip --
Way shorter in ABEL, but I'm a bit rusty there... Get yourself a webfitter
account from Xilinx, upload the design and let the webfitter run. 2 Mins
later you get a mail that you can download the JEDEC file (or need to
correct some errors I overlooked due to the late hour).
Rainer
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