From: Laze Ristoski (lazeristoski_at_veenstaete.nl)
Date: 2004-01-07 16:19:13
Hi, Someone posted a thread at CSDb, and he says that he noticed 8 cycle variance when an IRQ is generated. To be more precise, as the current instruction must be finished before jumping to the IRQ, there will be cycle jitter. When using _legal_ opcodes, the jitter should move in range from 0-6 (7 cycle variance). But in fact, there's 8 cycle variance (no badlines or sprites!) This feature also happens in CCS and VICE, so there must be an explanation. Try setting an IRQ at rasterline $ff (or at any place where there's no badline). In the main loop use the following code: loop: inc $c000,x ;(or another address, but there should be no page-crossing) bpl loop bmi loop Can anyone explain where the 8th cycle comes from? There's also another thing: when a raster IRQ occurs, the minimum cycle at which the first instruction executes is 12 (counting the cycles from 1-63). The IRQ condition is given in cycle 1, right? There's 7 cycle delay between the IRQ occurrence and the cycle at which the first instruction of the IRQ is processed. If we use NOPs in the main loop, there will be minimum of 2 cycles delay + 7 cycles for the IRQ. So cycle 1 + 2 + 7 = 10. Why does it appear to be 12? Maybe I've done some mistake, but I'd appreciate if someone can explain what exactly happens when a raster interrupt occurs. Thank you! -- Cybernator Message was sent through the cbm-hackers mailing list
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