From: Oliver Achten (achten_at_gmx.de)
Date: 2003-08-20 23:01:56
Dear Todd,
> This is only when a specific memory range is mirrored. If a write occurs
> to
> RAM that isn't mirrored, the SuperCPU doesn't write to the cache
> simultaneously. There are a variety of mirroring options. This way, the
> SuperCPU is sped up to a certain extent and optimized for the particular
> use
> of memory and graphics. Writes always happens to I/O, regardless of
> mirroring schemes used. The mirroring schemes are complex and it would be
> easier to build a system for the c64 accellerator that will simply mirror
> everything at the expense of speed.
Do you think the speed gain would still be visible ? Perhaps disabling
mirroring for $0000 - $01ff could be integrated, since these locations should be
used most by applications. Are there any programs which use these memory
locations for graphics storage?
> > So what about the $00/01 location? It can´t be accessed by any external
> > device, so how could the SCPU do the trick turning on/off the char- or
> the
> system
> > Roms?
> >
> >From my understanding, the SuperCPU tristates the host CPU and this is
> done
> via $00/$01, I believe. Once the host CPU is disabled, the SuperCPU copies
> the char and system rom's to the faster onboard SRAM and runs off from the
> SRAM. Next, the SuperCPU emulates the myriad c64 configurations of $00/$01
> via a CPLD or FPGA chip called Altera. This is why there is a slight delay
> when the c64/128 boots up with a SuperCPU accellerator, as the SuperCPU is
> busy copying stuff off from the host CPU system and setting up a system to
> run off pretty much entirely from the accellerator.
So this would also include re-implementing the PLA on the accelerator due to
the lack of external PLA signals.
> I misunderstood you earlier. Now, it appears you're trying to build an
> accellerator right into a C64 unit, replacing certain parts, etc. and not
> building a cartridge-based solution. That sounds okay to me, but I would
> guess that the vast majority of the CBM hobbyists here would prefer a
> cartridge solution for an accellerator as they don't want to take their
> machines apart, desolder chips, etc. Either way you do it, I hope you are
> able to realize a simple c64 accellerator and it is a cool project to do.
Thank you. Actually, thinking about it twice, the external solution seems to
be more elegant. I actually didn´t look at the SCPU so closely, because i
thought it is much too complicated for a home-build project. But now, since i
understand its internals much better, i am beginning to favour this solution,
especially since i didn´t thought that it would generate so much reponse (i
always thought most of you guys here have a SuperCPU anyway).
So perhaps a low-profile SuperCPU could look like the following:
-64K high speed SRAM for caching the C64 area.
- 128K 29F010 ROM (55ns -> no delay) for BIOS/OS.
- 1 byte write cache
- mirroring disabled for $0000 - $01ff for faster execution
- expansion connector for hardwrare additions
- perhaps a socket for a 512K sram chip?
Have a nice day!
Oliver
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