RE: 3.3V interfacing to the CBM

From: Gideon Zweijtzer (
Date: 2002-12-10 10:44:25

Hello all!

I got this whole list of items on this particular issue, and a lot has
been said already. I will complement this with my experience that I had
attaching my FPGA-6510 to a real C-64 board.

a) The C-64 uses TTL, that means that your 'high' output of your 3.3V
device is sufficient to be recognized as a '1', since TTL has a Vih of
only 2.0V.

b) Make sure to use a CPLD/FPGA that is 5V tolerant on the inputs.

c) Use series-termination resistors for every output, because the old
TTL stuff is very slow, bus loads usually very very high, and the layout
of the board is not designed to handle very steep edges on your outputs.
These very steep edges introduce a significant amount of ground bounce
(I have measured up to 2V peaks between one ground point on the main
board and another!!!). Needless to say, this ground bounce effect
distorts all logic levels and generates a huge amount of electromagnetic
emission. The latter you are probably not interested in so much, but the
ground bounce and crosstalk effects are going to be a serious problem! I
recommend using something like 68 Ohms in series with your outputs, and
place these resistor(packs) of course as close as possible to the output

With kind regards,

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