Date: 2002-12-10 07:37:33
Hello Spiro, >> Seems most new LSI technology is going to 3.3V designs (eg CPLDs etc). Most >> are input tolerant for 5V, but how does one interface their outputs? Does a >> simple pull-up resistor to 5V do the trick? >as CMOS can run with a Vcc in the range of 3V to 15V, I think that a CMOS >buffer should do the trick. Since the 4049 or 4050 is very tolerant of >the input, so you can use it to interface higher voltages than its Vcc, >I'm used to use them as buffer. In your case, these should do the trick, >at least the HCT types (74HCT4049, 74HCT4050), although I never tested it. My only worry about this method is that if my objective of using a CPLD (36 or 72 macrocell device) is to reduce chip count, then it is all kind of defeated by having to buffer the outputs.... Some Xilinx chips were 5V originally, but the supply I was to go through only sells 3.3V boards/chips..... - Nick PLEASE TAKE NOTE: The contents of this email (including any attachments) may be privileged and confidential. Any unauthorised use of the contents is expressly prohibited. If you have received this email in error, please advise us immediately (you can contact us by telephone on +61 8 9441 2311 by reverse charge) and then permanently delete this email together with any attachments. We appreciate your co-operation. Whilst Orbital endeavours to take reasonable care to ensure that this email and any attachments are free from viruses or other defects, Orbital does not represent or warrant that such is explicitly the case (C) 2000: Orbital Engine Company (Australia) PTY LTD and its affiliates Message was sent through the cbm-hackers mailing list
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