RE: 3.3V interfacing to the CBM
Date: 2002-12-10 07:37:33

Hello Spiro,

>> Seems most new LSI technology is going to 3.3V designs (eg CPLDs etc).
>> are input tolerant for 5V, but how does one interface their outputs? Does
>> simple pull-up resistor to 5V do the trick?

>as CMOS can run with a Vcc in the range of 3V to 15V, I think that a CMOS
>buffer should do the trick. Since the 4049 or 4050 is very tolerant of
>the input, so you can use it to interface higher voltages than its Vcc,
>I'm used to use them as buffer. In your case, these should do the trick,
>at least the HCT types (74HCT4049, 74HCT4050), although I never tested it.

My only worry about this method is that if my objective of using a CPLD (36
or 72 macrocell device) is to reduce chip count, then it is all kind of
defeated by having to buffer the outputs.... Some Xilinx chips were 5V
originally, but the supply I was to go through only sells 3.3V

- Nick


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