From: Michael Huth (520052975648-0001_at_t-online.de)
Date: 2002-10-03 10:45:17
At 20:21 02.10.2002 +0200, you wrote:
>>Are the bit errors some chip bug?
>
>How did you connect the two CIAs? Just a direct connection without any
>active hardware in there? Since the CNT and SP outputs have open collector
>drivers, the L to H rise time is extremely slow, typically in the range of
>one microsecond. Since the switching point is not clearly defined on the
>voltage scale, it could happen that the CNT transition is detected when
>the SP signal didn't become stable yet. You can improve this by adding a
>LS14 Schmitt trigger gate before the inputs of each CIA, and inverting the
>output with a 7406. Just have a look into the 1571 schematics, it is done
>exactly this way in them!
I am not really the man for the hardware, I do mainly the software. I
uploaded the Layout to
http://520052975648.bei.t-online.de/ssi-interface.png
I guess it is done the way you described above.
I'm just wondering if it is possible to get a stable transfer with TA =
$0001 with a 1Mhz CIA ?!?
Regarding the cable Benjamin (the hardware guy) wrote, the runtime delay of
the driver ICs are about 2-10ns , the signal runtime on the cable is 2ns,
while half a CNT period is 2µs. The reflections and runtime delay is
neglectable.
@Marko: I will try the IN/OUT Flag trigger for shift register reset as soon
as I get access to the hardware again )
Ciao...
...Micha
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