# RE: Reverse engineering logic equations from truth tables

From: Gideon Zweijtzer (gideonz_at_dds.nl)
Date: 2002-06-24 14:36:52

```Marko wrote:
|Okay, that's just a different way of putting it.  But I would expect a
|VHDL tool to crash if it was fed 2^20=1048576 lines like that.
|Want to give it a try?

Well maybe. 65536 lines should be okay - although it would take long. 20-bit
is already a lot trickier. I would love to give it a shot for the C-64 PLA
and see if the equations are similar to what people on this group have
found.

|I haven't done any VHDL stuff, and I don't have easy

|Converting the binary data to your proposed format or to CNF or DNF is
|straightforward with a few lines of Perl or C.

I agree.

|> If you want to improve readability, you can replace the words inputvector
|> and outputvector to a set of signal names that are actually used on the
|> Commodore board.
|
|Yes, but labeling doesn't eliminate "don't care" variables or reduce the
|number of terms in a CNF or DNF equation, which is (in my opinion) the
|main reason of unreadability.  In the worst case, each output can be a
|function of all 20 inputs (I'm assuming that the C128 PLA has 20 inputs).

Of course I am talking here about the *reduced* equations, not the original
generated equations.

Anyway, if you don't have access to commercial VHDL tools, you could always
write a little program that does the logic reduction for you. The algorithm
is not that complicated (as long as you don't want to find an optimal use of
temporary nodes; i.e. reuse of some partial logic equations. In other words:
straight from input to output is relatively simple). My initial reason to
binaries to equations is time consuming and prone to mistakes. Better let a
computer do it for you, right? (Maybe I am just too lazy ;)