From: Gideon Zweijtzer (gideonz_at_dds.nl)
Date: 2002-04-22 10:58:03
|I tried to post this e-question before, but my sender-address was wrong,
|therefore the e-mail was bounced. This one should work...
|What did you do with the two-phase clock ?
Some documentation on the 6510 states that the chip needs two
non-overlapping clocks. Ruud Baltissen pointed out that this is *NOT* true;
the CPU just outputs its input clock (PHI1) with some delay to the output
PHI2. [I found some other documentation that confirmed this.] I make this
PHI2 clock by filtering (and thus delaying) PHI1 and feeding it into the
FPGA. The FPGA outputs it to the PHI2 pin. Internally I use the inverse
clock to run all the state machines (that is equivalent to the falling edge
of PHI2.) So I don't use the other clock edge.
I hope that this answers your question. :)
Greetz,
Gideon
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