Date: 2002-04-16 15:34:25
Hallo allemaal, I know it took ages to write this doc but I run into something that took days to understand. I wrote the original in Word. Unfortunately the conversion removed all identions. I would like some comment on the technical facts. On the end I would like someone to correct linguistic errors. ============================================================ 8088-board for the B-series This document describes the working of the 8088 coprocessor board that enables Commodore B-series computers like the CBM 610, 710 and 720 to run CP/M86 software. Basics The most important IC's on the board are: - 8088 - 6525 - 6526 - AM9128, a 2K*8 SRAM The basic idea IMHO is that the 8088 runs parallel to the 6509. Either the 8088 or the 6509 has access to the onboard main DRAM. The 8088 has NO access to the video-RAM or onboard I/O. This includes the video IC. The 8088 communicates with the 6509 using the 6525. The 6525 is connected to the 6526 through the complete A-port and partly the B-port. The 6526 on its trun is controlled by the 6509. The SRAM is controlled by the 6509 as well. My idea is that this is the place where the 6509 resides when the 8088 controls the main DRAM. These 2 KB of SRAM can be found at $00800/$00FFF. This means that the 6509 has no access to the stack. I already wondered if these 2KB were sufficient for the 6509 to perform all tasks the 8088 wants it to. With the task I mean things like diskaccess or an update of the screen. But having no access to the stack I really doubt that. (AFAIK the 6509 has not a relocatable stackpointer) The onboard I/O For those people not that familiar with a 8088, this CPU has a sepperate memory- and IO-addressrange. The 8088 also can be used in two modes. In this case it is used in the so-called MAX-mode and that simply means that certain signals are outputted by a a sepperate IC, the 8288 in this case. Important to know is the this system has a sepperate I/O-read, I/O-write, memory-read and memory-write signal. Beside the 6525 the 8088 also controls a 8259 Programmable Interrupt Controller. At the base of the selection of these IC's we find a 74LS138 3-to-8 multiplexer. The 138 is enabled by an AND-gate, U18c. This gate ANDs the I/O-read and -write signal. The 8259 can be found in the addressrange $xx00 - $xx1F. It is connected to the 8088 as can be expexted. The 6525 can be found in the range $xx20 - $xx3F. The way it is connected to the 8088 is quite unfamiliar. The output of the 138 is negated through a 74LS04-invertor, U21f, and the result is fed to the Preset-input of a 74LS74 Data-flipflop, U29a. The Q-output enables the 6525. The /Q-output feeds the data-input. The moment the 8088 addresses the 6525, the Preset is released. The first positive edge of CLK then enables the 6525. The next would disable it again. For those able to lay hands on a datasheet of the 8088 and 8288: that would be the raising edges of phase T2 and T3. I don't see any problem for a write operation here. But during a read-operation this would mean the data-output of the 6525 is disabled long before the point the 8088 reads the data: the falling edge at the end of T3. The BIOS The BIOS can be found inside a 2532 EPROM, U14. A 74LS373, U8, latches the addresslines A16..19. U10a, a 4-input NAND-gate, NANDs the corresponding outputs. Its output is inverted again by U21c (74LS04). The result is NANDed (74LS00, U19c) with the inverted (74LS04, U20e) memory-read signal, outputted by the 8288. The output of the U19c enables the EPROM. What you need to know about the B-series /BUSY1-output. The /BUSY1 output is generated by the Q-output of U57, a 74S74 Data-flipflop through U96a, a 74LS05 OC-invertor. The Preset-input of u57 is fed by the reset-signal. The Clock-input is fed by CLK1. The Data-input is fed by PB4 of the 6525. The Clear-input is fed by /BUSY2, which originates from the 8088-board. Refresh-signal for the DRAMs. CLK1 clocks U89, a 393 double 4-bit counter. U88c, an AND-gate ANDs the outputs 2QA and 1QC meaning it outputs a (H) after 24 clockcycles. This signal is used to block CLK1 to U89 using U54, an OR-gate. This signal is ANDed with the 6509's SYNC-signal using U88b, an AND-gate. This means U88b outputs a (H) at the beginning of the first instruction after those 24 clockcycles. U88b's output is fed to the data-input of a 74LS74 D-flipflop, U53. U53 is clocked by CLK1. Output Q drives a 7496 Open-Collector invertor that on it turn drives the RDY-input of the 6509. The /Q-output is NANDed (U56a) with the /P2REFGRNT signal (see later). This output is labeled REFEN (IMHO: REFresh ENable, see next block). REFEN clears U89 allowing the 6509 to perform another 24+ cycles. The Clear-input is directed by the BUSY2-signal. The moment this signal is active, the signal coming from U89/88 is ignored ie. then only /P2REFGRNT counts. U88b's output is inverted by an 74S05 OC-invertor, U96. The result is the signal /P2REFREQ (Processor 2 REFresh REQuest). If the second processor grants this request, it negates /P2REFGRNT. Negating /P2REFGRNT means that REFEN becomes (H), regardless of what the other input of U56a does. So I can imagine that /P2REFGRNT only is negated when /BUSY2 is active (L). Addressing the DRAM, found on the left side of sheet 3: The signals MUX and /MUX are generated by the same 74LS74 data-flipflop, U82. U82 is clock by the DOT-clock. Its data origins from a 74S299, a counter. U91, a 393 double 4-bit counter, generates the refresh-address and is clocked by the signal REFEN. MUX and /MUX are ANDed with /BUSY2. The results are NORed with REFEN and fed to the A/B-inputs of some 74S153 4-to-1 multiplexers. Conclusion: /BUSY2 decides wether the eternal addresslin EXTMA0..7 (/BUSY2 = L) or the CPU-addresslines (/BUSY2 = H) are fed to the DRAMS. When (H), MUX and /MUX also decide wether it are the addresslines 0..7 or 8..15 that are fed to the DRAM. REFEN overules the previos signals. When active (H), the refresh-address is fed to the DRAMs. Enabling the U8, the 74LS373 Wether the 8088 or the 6509 controls the system is reflected by wether the output of U8 is enabled or not. So by finding out what enables U8, we have an idea how the 8088 is granted access to the whole system. U8 is enabled by U19b, a 74LS00 2-input NAND-gate. This means BOTH inputs must become (H) for enabling U8. Pin 5 is fed by the Q-output af U22b, a 74LS74 D-flipflop. This same siganl is also the P2REFREQ-signal described above. The Clear-input of U22b is directed by the /BUSY1 output described above. The signal is fed as well to PB0 of the 6525 and PB0 of the 6526. The Clock-input is directed by PC5 of the 6525. The data-input is tied to GND, so the only way the Q-output can become (H) is negating the Preset-input. This input is directed by PB6 of the 6526 via two 74LS04 invertors, U20d and U21e. The output of U20d is fed to the 8259. This means that when the 6509 enables the 573, thus enabling the 8088 to control the DRAM, an interrupt is generated. Conclusion: Only the 6509 is capable of granting the 8088 access to the main DRAM. But both the CPU's can revoke the access again. Remark What is the state of this flipflop after a reset? Pin 4 of U19b is fed by the Q-output af U26b, also a 74LS74 D-flipflop. The Preset-input is directed by U18a, a 2-input AND-gate. Pin 2 is fed by the Reset-signal coming from CBM motherboard. Pin 1 is directed by U20f, a 74LS04 invertor, which on its turn is directed by U24d, a 74LS86 EXOR-gate. Pin 13 of the EXOR-gate is directed by the Q-output of U23b, a 74LS74. The clock-input of U23b is fed by an 74LS04 invertor, U21a, which on its turn is fed by the CLK-signal generated by the 8084. The data-input of U23b is fed by the Q-output of U23a. Clear and Preset are tied to +5 V. Pin 12 is fed by the Q-output of U23a. U23a is clocked by the ALE-signal coming from the 8288. The data is coming from U19a, 74LS00 NAND-gate. This signal is inverted by U23a, an EXOR-gate, and fed to the Preset-input. U19a pin 2 is directed by the Q-output of U22b (see above). Pin 1 is directed by the /Q-output of U22a. U22a is clocked by the output of U21a (= inverted CLK). The data- and Clear-input are fed by the P2REFREQ-signal coming from the 6509-board. The way the EXOR-gate is connected to U23a and U23b means that it outputs a positive pulse everytime U23b changes state. The data-input is fed by the Q-output of U26a. The Preset-input of U26a is fed by U18a (see above). The Clock-input is fed by U20b, a 74LS04 invertor. The input of U20b is held (H) by a pull-up resistor and is connected to output 2Y2 of U25, a buffer. U25 is enabled by U20f, see above. 2A2, the input for 2Y2 is connected to Ground permanently. So the result is that when U20f enables U25, U26a is clocked. Now it gets more difficult. The input of U20b is also connected to pin 31, one othe two Request/Grant-pins of the 8088. These pins can serve as well as inputs as outputs. Feeding this pin with a pulse causes the 8088 to release the bus for a moment and it signals this with sending a negative puls itself out of this pin. The fact is that is that there is no reason for the 6509 to ask the 8088 to release the bus as the 6509 has no connection at all with its bus. But on the other hand the pulse outputted by the 8088 causes U26a to output a (L) at its Q-output. Now let's have a look at this circuitry from the side of the 6509. If the 8088 is in charge, a request for Refresh will negate U22a's /Q-output. On the end this will cause the invertor U20f to output a negative pulse. This pulse will enable U25 to give a negative pulse to U20b what will result in a positive pulse for U26a. This negative pulse will negate output Q. BUT..... The pulse coming from U20f will negate U26a's Preset-input causing output Q to become (H). And that contradicts with the previus line. The above caused an enormous delay producing this document because at first I thought that I had make a mistake with the drawings. Then I realised that the 8088 outputs pulses as well AFTER the initial pulse caused by the request. these pulses don't reach the Preset-input so now Q becomes (L) indeed. This value is clocked by U26b which on it turn disables the 373 and enables U27a to negate the RAS output towards the 6509 board. The moment U8 is NOT enabled, the inputs of U10a float. A TTL-input sees this as a (H). So I presume that the moment this is happening, the 8088 resides in the EPROM. RAS and CAS signals The AND-gate U10d combines the MEMW and MEMR signals. U10b is used to combine the result with the output of U27a (see above) to create the final RAS-signal. When there isn't a memory access, an invertor, U20c, negates the Preset-inputs of U27b, U28a and U28b. The output of the last one is the CAS-signal towards the 6509 board. When there is an memory access, the data-input of U27b is negated. The clocksignal at the OSC-output of the 8284 then clocks the value to the Q-output of U27b. This value is then cascaded to U28a. The Q-output directs the 74LS257 multiplexers U11 and U12. This value is cascaded again to U28b. And its output is the CAS-signal as mentioned above. Both clock-inputs of U28 are clocked by the inverse OSC-signal. ___ / __|__ / / |_/ Groetjes, Ruud \ \__|_\ \___| http://Ruud.C64.org Message was sent through the cbm-hackers mailing list
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