Hallo allemaal,
At this moment I'm working on a description af Bo's 8088 board. I would like
to have a second opinion on this text:
The 6525 can be found in the range $xx20 - $xx3F. The way it is connected to
the 8088 is quite unfamiliar (at least to me). The output of the 138 is
negated through a 74LS04-invertor, U21f, and the result is fed to the
Preset-input of a 74LS74 Data-flipflop, U29a. The Q-output enables the 6525.
The /Q-output feeds the data-input. The moment the 8088 addresses the 6525,
the Preset is released. The first positive edge of CLK then enables the
6525. The next would disable it again. For those able to lay hands on a
datasheet of the 8088 and 8288: that would be the raising edges of phase T2
and T3.
I don't see any problem for a write operation here. But during a
read-operation this would mean the data-output of the 6525 is disabled long
before the point the 8088 reads the data: the falling edge at the end of T3.
The above conclusion would mean that the design cannot work. But it does, so
I am wrong. But where ???
FYI, the SCH can be found at: http://home.hccnet.nl/g.baltissen/8088.gif
Thank you for your time.
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/ __|__
/ / |_/ Groetjes, Ruud
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\___| http://Ruud.C64.org
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