Hi Nick!, email@example.com wrote: > > Whilst the 5717 chip is waiting to read the "sync" going low, what is it > doing with the line that is connect to the same POTX via the resistor? Is it > being driven low, hi or held in the MOS equivalent of O/C? I couldn't measure this myself since I never had a 1351 (Frank Kontros did some measurements for me instead :-) ). The patent document must have had something about this. (As I noticed, Delphion has dropped providing free download service, so the 1351 patents aren't freely available anymore :-/. I have the patents somewhere -- I've saved them onto a CD, should I post them tomorrow?). I'd say the outputs are left floating. At the end of the 512 cycles long process, in cycle #480, the 5717 stops driving both POT outputs (I clearly remember this, I even noted it somewhere in the mouse interface document). Will it sometimes still drive the outputs? I don't know but the patent didn't mention anything like that. (I'm sure you're thinking about the first startup of the circuit -- how on Earth will the process start, if the POT line is constantly at low level -- or, how will it rise to +5v if nothing pulls it up. I don't know. I remember setting both POT outputs to drive the lines in my design, to ensure startup). Best regards, Levente Message was sent through the cbm-hackers mailing list
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