I want someone to verify the remote possibility of this working. it sounds like it would, with the limitation of not changing rows in the memory in question: Phase 2: DMA We prepare address and place it, unmultiplexed on the bus C64 sets up Row address, toggles RAS c64 sets up Col address, asserts CAS for data read/write we grab the byte we change the low byte of the address to addr+1 we change the high byte of the address to a known non-ram area (I/O, kernal, (above two happen at the same time) whatever) We change the high byte back, which causes the PLA to re-assert CAS. we read the next byte. end of phase 2/dma -- Neat idea, but there's just not enough time in 500ns to do it on a c64 clk->caslo is 229ns max PLA propogatoin is 80ns max ras precharge 80ns cas precharge 40ns clk->cas 229ns cas->casram 80ns casram->data 50ns (150ns ram) cas->casram 80ns casram->data 50ns (150ns ram) ====== total 489ns I suspect I got the process from Highlander (hld)/FLT, as he had a highspeed write plan. However, I cant remember. The calculations below are from a conversation between Bogax and I on irc. I stumbled upon this while mucking about in my website. Please let me know what you think (via the mail list). Message was sent through the cbm-hackers mailing list
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