16 MB REU clone again

From: Konrad Buryło (K.Burylo_at_elka.pw.edu.pl)
Date: 2001-09-04 16:38:57


As I'm finishing my Master Thesis now I don't have too much time to check
CBM-Hackers list regularly. Today I've read that 16 MB REU clone thread -
you guys considered using either CPLD or FPGA.
I'm for FPGA - especially Xilinx Spartan2 series that I've used at work
(XC2S100-PQ160 and bigger ones :) ). I don't have too much experience with
Altera ones  - but AFAIK there is no free (and usefull in the same time)
software for Altera FPGAs. MaxPlus which you can download from Altera is
quite limited (although its easy to convince it to be a full, non-limited
version :) ).
You talked about clock-doubling - in Spartan2 family its easy. Spartan2
FPGAs contain DLLs (Digital /Phase/ Locked Loops). We used them to generate
80 MHz clock driving an external A/D converter and internal FIFO. DLLs can
generate x2, x4 and x8, divided clock (/2) and 4-phase clock.
Spartan2 has also integrated memory blocks, which are configurable (can be
single or dual port RAM with different width/length) and are usefull if you
want to build eg. FIFOs .
The second thing - configuration. Spartan2 (in fact - no FPGA starting from
XC4k) doesn't have master-parallel configuration mode (which needed normal
8-bit wide externel memory - EPROM etc). But there is a fast slave-parallel
mode (8bits parallel with max. 50 MHz clock). Master-serial mode is much
slower and we didn't used it (mainly due to serial configuration memories,
we wanted flexible, reconfigurable design). You can always use CPLD as a
configuration controller (fast, but expensive).
The cheapes method is to configure FPGA from the main processor (6510) - but
we should change C64 initialization (need a cartridge with Flash/Eprom).
Here in Poland intel 8051 is so popular :( that all people I know use it to
configure FPGAs...
As soon as I finish Uni (in about 1 month) I'll be able to help you with
work (FPGA stuff, programming, PCB design etc). I also want to convert some
of my older projects to FPGAs. My IDE controller now use GAL+646+245,
hardware breakpoint  use a whole bunch of comparators (I've done this as an
add-on to Action Replay - always needed breakpoint on memory access (BPM -
for SoftIce guys) ).


P.S. Anyone has checked that new Xilinx WebPack ISE 4.0 ?

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