Ruud Baltissen wrote: > > Your remark made me remember that I still want to have a look at the free > core at http://www.opencores.org/ only to find out that it isn't there > anymore (or am I looking at the wrong place?). > You're looking in the wrong place. It's at http://www.free-ip.com/6502/... > If it is gone, is yours available to have a peek at to see what VHDL looks > like and how "programming a 6502" is done, please? > Unfortunately it's far from beeing synthesizable yet. Basically, it's just a collection of pieces that hasn't been fit together yet, so I don't think it would give you much. Also, I haven't made up my mind on whether I want to release that information publically or not. There's quite a few hours of hard work behind it... But if you only want to see an example of what it looks like, here's a piece of code from the ALU: -- -- ALU stage 2 handles the 2 operand operations OR, AND, XOR, Add, Compare -- and Subtract and derives the flag outputs. -- It is implemented as a 4-bit unit, 2 are needed for a full byte-width ALU -- architecture ALU2 of ALU2 is constant fcnOR : std_logic_vector(3 downto 0) := '1000'; constant fcnAND : std_logic_vector(3 downto 0) := '1001'; constant fcnXOR : std_logic_vector(3 downto 0) := '1010'; constant fcnAdd : std_logic_vector(3 downto 0) := '1011'; constant fcnCmp : std_logic_vector(3 downto 0) := '1110'; constant fcnSub : std_logic_vector(3 downto 0) := '1111'; -- Operations are carried out using 5 bits (4 bits + carry): signal opA : std_logic_vector(4 downto 0); signal opB : std_logic_vector(4 downto 0); signal opC : std_logic_vector(4 downto 0); signal result : std_logic_vector(4 downto 0); signal bcdRes : std_logic_vector(4 downto 0); signal useBcd : std_logic; signal fcn : std_logic_vector(3 downto 0); begin opA <= '0' & dataInA; opB <= '0' & dataInB; opC <= '0000' & carryIn; fcn <= aluEnable & fcnSelect; with fcn select result <= opA or opB when fcnOR, opA and opB when fcnAND, opA xor opB when fcnXOR, opA + opB + opC when fcnAdd, opA - opB when fcnCmp, opA - opB - ( opC xor '00001' ) when fcnSub, carryIn & dataInA when others; -- Form BCD adjusted result bcdRes <= result + X"6" when (result > X"9") else result; -- Output BCD-adjusted value? useBcd <= '1' when (bcdEnable = '1' and ( fcn = fcnAdd or fcn = fcnSub )) else '0'; -- Evaluate dataOut dataOut <= bcdRes(3 downto 0) when (useBcd = '1') else result(3 downto 0); -- Evaluate carryOut carryOut <= bcdRes(4) when (useBcd = '1') else result(4); -- Evaluate zero output zero <= '1' when (result(3 downto 0) = '0000') else '0'; -- Evaluate negative output negative <= result(3); -- Evaluate overflow output (only makes sense if fcn=add or sub) overflow <= opA(3) xor ( opB(3) xor result(3) ); end ALU2; -- Christer Palm Message was sent through the cbm-hackers mailing list
Archive generated by hypermail 2.1.1.