Re: VIC 26 Lines Bug - Truth or Legend ?

From: Konrad Burylo (
Date: 2001-08-17 22:13:29

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Sent: Friday, August 17, 2001 10:46 AM
Subject: RE: VIC 26 Lines Bug - Truth or Legend ?

> >I believe an data sheet states that the 6502 uses a dynamic design,
> whatever
> >this means... I always thought that this means that you cannot underclock
> >it...
> Could the two-phase clock be what makes it an efficient design, but if the
> internal delays for each micro-op is generated by an RC circuit then
> fall over... Only a hypothesis, but I agree with Ruud I can't see them
> having used a transistor-capacitor memory cell instead of a true flip-flop
> for their registers /latches?
> - Nick

Some facts:
1. NMOS 6502 uses a dynamic design  (minimum frequency exist). It doesn't
mean that every NMOS chip uses that kind of design.
2. CMOS versions are fully static (there is no minimum frequency). CMOS
chips can also use dynamic design (like some Paintiums...)
3. A dynamic design means there are no DRAM-memory cells instead of FFs but
boolean functions are evaluated in two phases - 1st for precharging
capacitors (in fact - parasitic capacitances), 2nd for function evaluation.
This way some boolean functions can use only one logic level - especially
extremely wide OR, AND - with more than a hundred of inputs. In a static
design single And-Or-Invert gate can't have more than about 5 inputs.


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