Hi Ruud, and others, I've also spent some time looking at the memory refresh issue with the larger SIMMs and think I've identified the best way to do this, all using a D-flipflop and two inverters for the refresh and 74257/258 for the multiplexing the additional 8address lines giving the C64 access to 16MB. Jameco still sell 16MB 30-pin SIMMs so hardware could be quite minimal. The trick with refresh is *not* to use the CAS-before-RAS scheme which seems to be the most popular approach from previous discussions, but to use hidden refresh, that is performing a CBR within a normal access cycle. This saves a lot of decoding and would on paper work because the larger DRAMS are also faster. Having had time to check the specs for the VIC-II at: http://highgate.comm.sfu.ca/~rcini/classiccmp/my_docs.htm it seemed feasible to divide the /RAS into two shorter pulses. As /CAS is left unchanged, the normal data access remains available for reads by either the CPU and VIC and meets their set-up timing requirements. The division of the /RAS signal is closely tied to a 4MHz signal derived from the 8MHz DOT clock, and hence is 125ns long (ie suits 125ns RAMs which is fast enough for most 30pin SIMMs). The only question mark I can see is that the worst case spec for the on-set of the normal /RAS generated by the VIC is 190ns after clocking reference which on some VIC chips might mean it gets missed.... The circuit needs it to be before 187.5Ns... but I'm figuring the propagation delays will work in our favour and it should be Ok (or a small RC on the inverter input can extend the delay). Timing and circuit are at http://www.64hdd.com/other/hidden-refresh1.gif http://www.64hdd.com/other/hidden-refresh2.gif How it works: The normal /RAS signal holds the D-ff in an inactive state whilst high, but when it goes low for a normal access, the D-ff acts as a divide/2 counter and two /RAS pulses are emitted each 125ns in width, before RAS goes high again. On some VICs the second pulse may get cut short to ~100ns. With this circuit only the RAS line needs to be intercepted. I haven't built it yet to prove that it works though, but logic checks out in a digital simulator. - Nick -----Original Message----- From: Ruud Baltissen [mailto:Ruud.Baltissen@abp.nl] Sent: Monday, 30 July 2001 7:27 PM To: firstname.lastname@example.org Subject: Update on my projects Hallo allemaal, I don't know who also monitors CommodoreOne and/or comp.sys.cbm so I give you the things I'm working on at the moment. 1) I realised a small board with a 65816, 6526A and some glue-logic capable of replacing a 6510. Last weekend I put three more ICs on the board and now I'm capable of using the full 16 MB range on a C64 !!! The idea is quite simple. First I detect if the 65816 addresses the first 64 KB segment or not using a 688 8-bit comperator and an invertor. The onboard I/Olines P0..2 are ANDed with the output of the invertor. This simply means that selecting any other then the first segment puts the C64 in RAM-only mode ie. I/O and ROMs are disabled. I already replaced my 4164's with 41256's but I am still have to add a 74LS157 or 257. Notice: _not_ the "A"-version. The idea is that when the VIC-II needs to access the DRAMs directly, it tristates the 257A's. The 157/257 outputs a (L) which means the first 64 KB segment of the 41256's are choosen automatically. You want to use the extra segments for other purposes? All you have to do is to disable the CAS-signal towards the DRAMs for the wanted range (it can be any size !!!) I intend to install 1 MB using four 30-pins SIMMs which means I need some more glue-logic. Question: I do have the pinouts of 30-pin SIMM's on paper somewhere :( Has any body them at hand in E-form, or a URL, please? 2) The day befor I went on hollyday I got the weird idea of connecting an IDE-HD directly to a 1541 using the three I/O ports of the 6522's: the free A-one and the two normally used for the diskcontroller. The only thing which has to be done is writing a new Kernal. Advantage: no complicated soldering/board needed. Spin offs: using a 1571, 4040 or 8x50 board as base. 3) In Poland I realised that the same trick can be performed with a C64: use the keuboard lines as databus and use the userport for the controllines. It took me 15 minutes soldering and about 45 minutes to make a nice hole in the side of the case to fit a connector for the HD in. Next step: writing some simple SW to see if this works at all. ___ / __|__ / / |_/ Groetjes, Ruud \ \__|_\ \___| http://Ruud.C64.org Message was sent through the cbm-hackers mailing list PLEASE TAKE NOTE: The contents of this email (including any attachments) may be privileged and confidential. Any unauthorised use of the contents is expressly prohibited. If you have received this email in error, please advise us immediately (you can contact us by telephone on +61 8 9441 2311 by reverse charge) and then permanently delete this email together with any attachments. We appreciate your co-operation. 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