Hallo allemaal, I know the VIC-II refreshes the DRAM's just by accessing them during CLK2=(L). But this cannot be a random access otherwise there is a risk that a row is not refreshed. So there must be a system. Regarding this system, how do the addresslines behave the moment RAS=(L) and CAS=(H) because this is the address to be refreshed? If the exact behaviour is known, I could make a scheme to generate other addresslines so one can use other types of DRAM like the 72-pins 8 MB-modules I have laying around. About the system, I expect some thing like "A0..7 increase every CLK2" or "A0..7 increase every second CLK2". In the first case I would increase (A8..x) every 256 pulses, in the second case I would toggle A8 every pulse and increase (A9..x) every 512 pulses. Thanks for any help. Groetjes, Ruud http://Ruud.C64.org - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tml.hut.fi.
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