Hallo allemaal, > The best I've ever come across is approx 1MHz read rate from the I/O area > on a PIII-600 using 8bit accesses. I expect the limiting case is not much > faster than this. Sitting in my car the answer suddenly occered to me. Although all boards have fancy IC's, IMHO somewhere deep inside reside two 8259s. To remain compatible with earlier systems they run on 2 MHz as all I/O does. But it depends on the number of cycles a CPU needs to perform an instruction. Looking at the specs of a 386 it only needs 2. That could explain the 1 MHz. The 8088 needs 4 so I/O runs at 500 Khz. But Nick wrote a little program and that told me that both my 486SX-25 and my IBM P3-800 run at 500 KHz as well. This I cannot explain. Now back to the interrupt. I was so focussed on how many cycles were needed that I completely forgot that EVERY hardware interrupt must end with a command to reset the flag for this INT inside the 8259. This simply means that this one, and AFAIK only, I/O commands will slow us down to the above 1 or even 0.5 MHz. Conclusion: I can forget my idea regarding this particular subject. No Spiro, I still won't tell yet :) Groetjes, Ruud http://Ruud.C64.org/ - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail firstname.lastname@example.org.
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