Re: 6510 banking question

From: Professor Dredd (
Date: 2001-05-04 23:26:09

Okay, it sounds like you're confirming what I

PLA controls which devices the 6510 can see in the map
CANNOT directly manipulate the PLA. A hardware RESET
signal applied to the PLA (technically -RESET, IIRC)
forces the banking logic of the PLA into the
ROML/ROMH/IO configuration.

R6510 is a 6-bit bi-directional I/O port on the 6510
chip. Bits 0-2 of R6510 control the banking inputs of
the PLA. -RESET forces the port to input mode and
clears the port data to $00 (just like the 6526). Then
the pull-up resistors bring the port to output mode
(referring to all 6 lines)

So, if I'm writing my own KERNAL, I can expect the
following conditions after every -RESET:

PLA configured to ROML/ROMH/IO
D6510 = all outputs
R6510 = $00

Hmm ... there seems to be a conflict here ... :-/

--- wrote:
> Hallo PD,
> > Is the hardware configured to ROML/ROMH/IO by the
> > RESET signal or does is depend strictly on IOINIT
> to
> > configure it that way?
> A RESET puts the onboard port in input mode. Some
> resistors pull the lines 
> (H). During IOINIT the 6510 programs pins as (H) and
> as output. AFAIK in 
> that order. 
> > The hardware that controls the banking function is
> in
> > the PLA right? I.E. R6510 is strictly a
> bi-directional
> > I/O register and the banking logic is external to
> the
> > 6510, right?
> Banking is setting a register which on the end
> enables a different part of 
> the memory. So IMHO the 6510 and PLA are both a part
> of the banking system. 
> The PLA is nothing more then a bunch of gates, _NO_
> flipflops, and does 
> nothing more then a kind of translation: a certain
> code on the input lines 
> leads to a certain code on the outputlines. You
> could say that the 
> 81S100-PLA is nothing more then a very fast ROM. 
> Groetjes, Ruud
> -
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