> The MEMW line becomes active (L) max. > 190 ns after the CLK for the 8237 becomes (H). MEMW becomes inactive again > 130 ns. after the next CLK becomes (H). This means it only lasts active (L) > for 190 ns. And that is not enough to cover the AFAIK min. I don't quite see where the 190ns comes from. Looks like the minimum low would be tCY - 190 + tDCW (or tDCR) (min) (but the data I have doesn't give minimums) Note 3 (Intel data sheet) says 'the net /IOW or /MEMW pulse width for normal write will be TCY-100ns and for extended write will be 2TCY-100ns' > I have no idea what cycle of the 4 MHz clock is seen as the first one. I can't answer that, I have presummed its the first cycle after an enable that occurs during an S0 (or were you talking about S0?), but surely, even with compressed timing, the first must be an S1 with ADDSTB high? ie you could look for ADDSTB bogax - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tml.hut.fi.
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