Since IEEE488 was originally the (proprietary) HPIB, you might be able to find useful info on the Hewelett-Packard site (I haven't looked) >From "PET and the IEEE 488 Bus (GPIB)" by Eugene Fisher - C. W. Jensen " ELECTRICAL FEATURES The electrical specifications in the IEEE Standard 488-1978, which are based on TTL technology, define electrical parameters such as data rate, bus length, voltage, and current levels at the interface connector. Data Rate The data rate sent on any signal line must be less than one megabit per second. Practical implementations of the bus operate from 5000 to 300,000 bits per second. Number of Devices and Cable Length The bus can have 15 or fewer devices connected to it at any given time. The inter-device cable length cannot exceed 4 meters. The total transmission length of the bus cannot exceed 2 meters times the number of connected devices, or 20 meters (65.6 ft.), whichever is less. Bus Receivers and Drivers Although the IEEE Std 488-1978 does not specify types of bus signal receivers or drivers, if these are designed with TTL logic, the specified signal levels can easily be achieved while meeting other requirements of the GPIB system. Signals are entered onto the bus as either active true or passive true values. By having open-collector drivers send signals into a terminated bus, active true values (the low state) can be made to override passive true values (the high state). The bus interface is so designed that conflicts between two devices trying to send opposite messages simultaneously over the bus can be resolved. The technique of active values overriding passive values is called the active transfer of a message. The specifications for such bus line receivers and drivers are shown in Table 3-1. Table 3-1. Specifications for GPIB line receivers and drivers GPIB Input GPIB Output True/False Logic State Voltage or Current (Receiver) (Driver) Minimum Maximum V low True 1 -0.6V +0.8V V high False 0 +2.0V +5.5V V low True 1 0.0V +0.4V V high False 0 +2.4V +5.0V I low True 1 -1.6mA I high False 0 +50uA I low True 1 +48mA I high False 0 -5.2mA While most bus signal driving circuits can be designed with tristate logic to attain higher data rates, the open collector configuration must be designed into drivers for signal lines SRQ, NRFD and NDAC.Also, during parallel polling, data lines DIO 1-8 must be driven with open-collector drivers. Typical Bus Interface Figure 3-4 is typical of the interface between the GPIB and bus devices. 0 Vcc=+5V +-5% | > _______________ < RL1=3.0K | | > +-5% | Receiver (2) | < | |\ | | | | \ | Driver (1) +---------------------+----| }------0 Data --> |\ | | | | / | | \ | | (3)| |/ | Data -->0---| }--+ | __|__ | | / | | / \ DC | |/ | | /___\ Clamping | | | Diode | +------+ | __|__ | | | | ___ | 100pf, __|__ > | _ | a _____ < RL2=6.2K | | capacitive | > +-5% |_______________| load on | < each signal | | line +------+ | __|__ ___ _ Notes: 1. Driver output current leakage: Open collector: +0.25mA max where VO=+5.25V Tristate: +- 40uA max where VO=+2.4V 2. Receiver input current: 1.6mA max at VO=0.4V 3. Typically, clamping diode is located within receiver component " bogax - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail email@example.com.
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