Clk2 is one-eighth of the DOT clock (that is Clk2 is derived from the DOT clock). The SuperCPU timing diagram shows the phasing relationship, or you could use the DigitalWorks expansion port simulator model off my website to verify. >From memory Clk2 goes high on the rising edge of DOT and also falls on the rising edge four DOTs later. Regards, Nick -----Original Message----- From: g.baltissen@hccnet.nl [mailto:g.baltissen@hccnet.nl] Sent: None To: cbm-hackers@dot.tml.hut.fi Subject: PC-card - DOT clock Hallo, I read several different stories about the DOT-clock so my two questions: - is the DOT-clock 8 times CLK2? (independent of PAL-or NTSC-system) - is the phase between CLK2 and the DOT-clock always the same? Thanks. Groetjes, Ruud http://Ruud.C64.org/ - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tml.hut.fi. PLEASE TAKE NOTE: The contents of this email (including any attachments) may be privileged and confidential. Any unauthorised use of the contents is expressly prohibited. If you have received this email in error, please advise us immediately (you can contact us by telephone on +61 8 9441 2311 by reverse charge) and then permanently delete this email together with any attachments. We appreciate your co-operation. Whilst Orbital endeavours to take reasonable care to ensure that this email and any attachments are free from viruses or other defects, Orbital does not represent or warrant that such is explicitly the case (C) 2000: Orbital Engine Company (Australia) PTY LTD and its affiliates - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tml.hut.fi.
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