Hallo Bogax, > sync on ADDSTB and insert S3s ? I own you all a big OOPS: I don't know how it happened but I simply missed the READY-input. This input plus 4 Mhz should give us an almost 1 MB/sec transfer. "Almost" because we loose a cycle every 256 bytes to update A8..15. (Something worth to filosophize about: C128's 2 MHz-mode ???) > synchronizing the 8237s cycles with the C64s timing The problem is that a synchronized 4 MHz signal does not mean that the produced read- and write-cycli are sunchronized as well. So I'll use two 573's to create a temporary buffer in the databus between the C64 and ISA-bus. Although actually not needed then, it worked fine in my first design. > Also, perhaps you could manage a memory to memory transfer at something > like 1.5 PHI2 cycles per transfer ie 3 cycles of PHI2 to move a byte I'm afraid that M2M transfer will stick at one byte for every two cycles. Unless we use two 8237's. I'm still playing with this idea because of the speed we gain but also the fact that I haven't worked out the scheme for telling the 8237 what byte goes/comes to/from to which part of the circuit during this type of the transfer. I'll explain: One bit should be enough to tell the circuit that an I/O-DMA goes to the C64 or to the ISA-bus it self. But with an M2M-transfer we have more possibilities: 1) C64 -> ISA 2) ISA -> C64 3) C64 -> C64 4) ISA -> ISA I didn't thought about the two last until now. Hmmm, writing down things sure help to clarify them as well, I am beginning to believe that a "simple" 74159 could do the trick :) And then we don't need a second 8237 (unless speed with M2M prevails). Groetjes, Ruud http://Ruud.C64.org/ - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail firstname.lastname@example.org.
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