On Wed, 4 Apr 2001, Spiro Trikaliotis wrote: > Did the VIC-20 (for example) have specific tri-state buffers which > did that? Then, possibly, this external circuit imposed another timing than > in the 6510 approach? Yes. Since the 6502 (in the VIC-20) has no AEC (Address Enable Clock) input that would tristate the address and data busses, like on the 6510 (in the C64), the data bus is buffered with a 74LS245, and the address bus and R/-W with some 74LS244s. Marko - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail email@example.com.
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