Re: SuperPET OS/9 MMU question

Am 28. Juli 2025 21:25:57 schrieb Rhialto <rhialto_at_falu.nl>:

> First some context, then some questions follow :)
>
> I have mentioned before, I think, that I am working on a PET core for
> the Mega 65. See https://github.com/Rhialto/PET2001_MiSTer/ and
> https://github.com/Rhialto/PET_MEGA65 . The published version is up to a
> 8296-D. -GD and SuperPET are in the works (including a 6702!).
>
> I ported some VIA test programs from VICE that were running on the
> VIC-20 to the PET, so that I could validate the VIA implementation that
> I was using.  It turned out I had to replace it, since it was failing
> too many of the tests.
>
> So I took another VIA (fortunately there were at least two others to
> choose from), the one from Gideon Zweijtzer. I made another change,
> because I was reminded by some other code I saw somewhere: looping back
> some outputs to inputs (in particular CB1 and CB2). After all, in the
> real hardware, those are connected with each other too, when they get
> connected to their single input/output pin. So I connected things up
> like so (in Verilog):
What do you mean that in the real hardware, CB1 and CB2 are connected to 
each other? They are not. CB1 is shift register clock, CB2 is shift 
register data, both independently either in or out, depending on internal 
vs external clock and data direction.

André