Re: The ROR bug - seems it wasn't a bug after all.

From: Ethan Dicks <ethan.dicks_at_gmail.com>
Date: Mon, 12 Feb 2024 11:50:54 -0500
Message-ID: <CAALmimk-FF1TcFdEhrAy3e0tGPRJ=EPBejoOp5hWCm0u7W0-3w_at_mail.gmail.com>
On Mon, Feb 12, 2024 at 10:39 AM A. Fachat <afachat_at_gmx.de> wrote:
> >> I know the 6551 has ... problems ...
> > I'd try to hook up a 16550 to a 6502 if I needed a UART for a new design.
>
> The 16550 is my default actually for many years now.

Are there any design "gotchas" that have to be considered (funny
timing stuff with Phi2 or stretching any timing signals) or do you
just plumb data bus and select to it?  I know the Z8530 has some
software timing issues (because you select a register with the first
write then use the register with the next access there's internal set
up time) but I wouldn't expect that from the 16550.

I've used them in x86 machines and I'd just like to learn if there are
any issues to be aware with connecting them to 65xx machines.

Thanks!

-ethan
Received on 2024-02-12 18:00:13

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