Re: How-to predict pending dummy read of 6502 CPU?

From: groepaz_at_gmx.net
Date: Sun, 15 Oct 2023 23:17:58 +0200
Message-ID: <4850651.GXAFRqVoOG_at_rakete>
Am Sonntag, 15. Oktober 2023, 21:03:01 CEST schrieb laughton_at_cyg.net:
> > Perhaps using one of the 6502 variants that indicate "next instruction"
> > on a pin is an option?
>
> groepaz, I'm only aware of one such variant, and that is the 65C816.  Is
> that what you had in mind?
>
> The '816 does wake up in 6502 "Emulation Mode," so perhaps it's suitable
> for Frank's needs.  And as you probably know, it has two outputs (VPA
> and VPD) which, when both low, reveal that a dummy cycle is in progress.
>   VPA and VPD get updated early in the cycle, same as the address lines.
> So, it's an early indication... but not quite a *prediction*.
>
> Hope this helps,

I was thinking of the SYNC signal that some 6502 or 65C02 chips expose on a
pin, this could be used to detect an opcode fetch, and to reset a counter that
counts the cycles into the instruction (which then allows to determine if its
a dummy cycle or not in a lookup table)

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Received on 2023-10-16 00:00:07

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