Re: How-to predict pending dummy read of 6502 CPU?

From: laughton_at_cyg.net
Date: Sun, 15 Oct 2023 15:03:01 -0400
Message-ID: <8dc3b8032007777b90dfbc63d2a80d32_at_cyg.net>
> Perhaps using one of the 6502 variants that indicate "next instruction" 
> on a pin is an option?

groepaz, I'm only aware of one such variant, and that is the 65C816.  Is 
that what you had in mind?

The '816 does wake up in 6502 "Emulation Mode," so perhaps it's suitable 
for Frank's needs.  And as you probably know, it has two outputs (VPA 
and VPD) which, when both low, reveal that a dummy cycle is in progress. 
  VPA and VPD get updated early in the cycle, same as the address lines.  
So, it's an early indication... but not quite a *prediction*.

Hope this helps,

Jeff  aka Dr Jefyll :)


On 2023-10-13 08:04, groepaz_at_gmx.net wrote:
> Am Freitag, 13. Oktober 2023, 13:55:12 CEST schrieb Frank Wolf:
>> Yes... this would work for single byte op codes and some stack related
>> operations
>> 
>> but not for some indexed operations where such a memory access (it's
>> actually
>> 
>> not only dummy reads but also some dummy writes) happens if there's a 
>> page
>> 
>> boundary crossing.
> 
> mmmh right, you'll need to keep track of the penalty cycles too.... 
> that makes
> it a bit less straightforward.
> 
> Perhaps using one of the 6502 variants that indicate "next instruction" 
> on a
> pin is an option?
> 
> --
> 
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Received on 2023-10-15 22:00:03

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