Re: How-to predict pending dummy read of 6502 CPU?

From: Frank Wolf <webmaster_at_frank-wolf.org>
Date: Fri, 13 Oct 2023 13:55:12 +0200
Message-ID: <eb19dc7a-8e75-4607-84b9-010cb03135cf_at_frank-wolf.org>
Yes... this would work for single byte op codes and some stack related 
operations

but not for some indexed operations where such a memory access (it's 
actually

not only dummy reads but also some dummy writes) happens if there's a page

boundary crossing.


I'd like to transparently manipulate the memory- of course omitting I/O

area where interrupt flags and such stuff gets cleared when there's an 
access.




On 13.10.23 13:40, groepaz_at_gmx.net wrote:
> Am Freitag, 13. Oktober 2023, 13:30:16 CEST schrieb Frank Wolf:
>> Hi!
>>
>> As many here know the 6502 actually fetches and discards the next opcode
>> when executing
>>
>> single byte instruction before actually fetching the OP code again and
>> it also write back actual
>>
>> data before writing the real data to a specific memory address; the so
>> called "dummy reads".
>>
>> Is there any easy way to detect or predict a dummy read? Maybe when
>> looking at some internal signals
>>
>> (e.g. Visual6502) without reimplementing the full instruction decoder?
> I'd just make a table with 256 entries, and in each entry use the bits to
> indicate those dummy cycles. That makes "is this a dummy cycle" a simple
> lookup based on current instruction and current cycle.
>
> What are you trying to do? :)
>
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Received on 2023-10-13 14:00:30

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