Re: Need help debugging IEC timing on #FujiNet

From: Imre Széll <iszell75_at_gmail.com>
Date: Wed, 5 Apr 2023 09:09:22 +0200
Message-ID: <CAHFX3ZNCTj2qbiUVW+AtNiGRRArTgY0sUpqzjYZJdY54w7QdvA_at_mail.gmail.com>
Gerrit Heitsch <gerrit_at_laosinh.s.bawue.de> ezt írta (időpont: 2023. ápr.
4., K, 20:10):

> On 4/4/23 18:40, Thom Cherryhomes wrote:
> >
> > What are the timing differences that can cause an absolute nightmare
> > between a c64 and a plus4? How does the 1541 deal with them?
>
> Besides slightly different (and, in the Plus/4, variable) CPU clock
> speed, VIC in the C64 has 1 badline per character line on the screen
> while TED in the plus/4 has 2 since it doesn't have a dedicated
> connection to a color RAM like VIC does and has to load the character
> codes AND color information from main RAM in 2 steps
>
> But a 1541 with standard ROMs will work reliably with a Plus/4. I'd take
> a look at the IEC code in the Plus/4 ROM to check for code that is used
> to adjust timings.
>

The plus/4 ROM uses the same timings for the IEC bus as the C64. The KERNAL
sets up TED timer #1 interrupt to handle bus timing and that is always
single clock so you don't have to deal with variable clock speed. The
timing is relaxed enough that the two TED badlines don't cause problems.

BR,
Siz
Received on 2023-04-05 10:00:04

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