Re: MOS process details?

From: tokafondo_at_tokafondo.name Date: Thu, 12 Jan 2023 19:33:34 +0000 Message-ID: <a8b79f14-3104-4703-bf72-dd59bc2bd796.maildroid_at_localhost>

There are documents in the team6502.org site that could help you.

-----Original Message-----
From: Nate Lawson <nate_at_root.org>
To: cbm-hackers_at_musoftware.de
Sent: jue., 12 ene. 2023 18:52
Subject: MOS process details?

I’m interested in the history of MOS and their processes used for various chips from calculators up through Amiga. I’ve read all the various books but I haven’t seen a list of their fab capabilities and which C= chips were made with each.

Apparently SID was 7 micron but VIC was 5 micron? What was the channel length? How did HMOS change this? Did they ever go to multiple metal layers? What was the wafer size and limitations? How did they use Applicon and CAD tools on each generation of chip? How did their processes compare to competitors at the time like Intel and TI?

Let me know if someone has more background on all this.

Thanks,
Nate