Re: Theorizing: chip select lines... (continued after mistake)

From: afachat_at_gmx.de
Date: Sat, 16 Jul 2022 20:43:32 +0200
Message-ID: <1822414.tdWV9SEqCh_at_euler>
On Donnerstag, 23. Juni 2022 01:37:25 CEST tokafondo_at_tokafondo.name wrote:
> 22 de junio de 2022 22:15, "Jesus Cea" <jcea_at_jcea.es> escribió:
> > On 22/6/22 21:24, tokafondo_at_tokafondo.name wrote:
> >> YIKES!!! I pressed 'sent' by mistake and didn't had completed the post!!!
> >
> > Remember than RAM is accessed twice per cycle: CPU and VIC-II.
>
> AFAIK, they both take turns when accessing memory. Only when VIC-II asserts
> BA/AEC low, it takes both turns for itself (badlines or sprite data
> fetching).
> > If I would design a fast 6502-like accelerator I would interpose a fast
> > cache (write thru with a small (maybe 1-2-4 bytes) write buffer) or,
> > using something like a 65816, fast and exclusive RAM in other banks.
> >
> > Dynamically adjusted 6502 frequency will not get you anything useful,
> > because 6502 do a memory cycle per CPU clock, always, even when not
> > useful at all. Too complicated, too little gain.
>
> One CPU cycles takes 500ns. Wouldn't be actually that useful that one CPU
> would take 125ns, so a 'batch' of four CPU cycles could be run while the
> VIC-II waits for its turn to take on memory again?
>
> I agree that it's too complicated to get it done, because now I'm realizing
> that if all the support chips (CIA, SID) are rated at 1Mhz, you wouldn't be
> able to mix several clock changes during those 500ns that the VIC-II waits
> for its turn for take on the bus again.

With a chip like the '816 that tells basically when it does bogus cycles, you 
can "hide" them inside the VIC-part of the 64's clock cycle. 

This is not complicated and has been done before (using CPLD).
http://www.6502.org/users/andre/pet816/features.html

If you want to use a fast NMOS (for undocumented opcode compatibility), that's 
probably still too slow, but an W65C02 can easily do that.
Also, on an NMOS, you'd have to monitor the bus cycles of the CPU and 
basically determine the internal state of the CPU to detect bogus cycles. Has 
been done before as well (e.g. KimKlone https://laughtonelectronics.com/
Arcana/KimKlone/Kimklone_intro.html )

André
Received on 2022-07-16 21:00:02

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