Awesome topic here guys! Why bother to implement a 6510 with a JTAG port bolted on, you ask? Why, obsessive completionism, of course! ...That, and the improved pin counts of less-obsolete IC packaging would allow the optional pins that were brought out on some variants of the 6502 core -- but had to be omitted from the 6510 due to pin-count constraints -- to be made available. I've no idea whether anyone might have a _use_ for any of them, but that's not really relevant -- it would finally be a "complete" 6510, in the sense that _every_ contemporaneous possibility (i.e., those that were always present _inside_ the IC packaging but inacccessible because of limited pin-counts) would be both implemented and available. I'm only _mostly_ joking about this concept, BTW -- I know that if there were any actual use cases for this project, they would likely be extremely uncommon, and those someone actually got around to building would be even rarer; but _all of the original design's inner potential would be COMPLETELY exposed for use_. After 40-odd years, such _satisfaction_! *swoon* In a vaguely related sub-topic... at one point, MOS optimistically produced a catalogue sheet projecting 65xx CPUs in speed grades up to 4 Mhz within the year. As we might lament, _they_ never managed it, though adding that feature to the "completist's 6510" would be straightforward enough. Edging from there into the dread realms of Feeping Creaturitis... we all know that nowadays the WDC offers base-level 6502-core devices at 16 MHz, and even 30ish years ago, CMD were able to hand-pick samples reliable at 20 MHz; I would be startled if no further potential has been realized since. Imagine doing a _proper_, 6510-based SuperCPU-alike that didn't need all those fiddly workarounds in the design! (...What is this "obsessiveness" of which you speak? Pfft, the nonsense some people will tell themselves! *grin*) Gordon "gsteemso" Steemson > On Jun 22, 2022, at 2:31 PM, Jesus Cea <jcea_at_jcea.es> wrote: > > On 22/6/22 13:07, tokafondo_at_tokafondo.name wrote: >> Let's say that someone patches an emulator or fpga'ed 65xx cpu and exposes its internal registers. > > Modern CPUs, even dirty cheap microcontrollers, have JTAG capabilitied: breakpoints, instruction single stepping, read/write of internal registers. Only 4 pins needed, 2 if you share VCC and GND (cJTAG variant). > > Nevertheless, I don't see the point for a C64, beside debugging and that would be a very small market. > > -- > Jesús Cea Avión _/_/ _/_/_/ _/_/_/ > jcea_at_jcea.es - https://www.jcea.es/ _/_/ _/_/ _/_/ _/_/ _/_/ > Twitter: _at_jcea _/_/ _/_/ _/_/_/_/_/ > jabber / xmpp:jcea_at_jabber.org _/_/ _/_/ _/_/ _/_/ _/_/ > "Things are not so easy" _/_/ _/_/ _/_/ _/_/ _/_/ _/_/ > "My name is Dump, Core Dump" _/_/_/ _/_/_/ _/_/ _/_/ > "El amor es poner tu felicidad en la felicidad de otro" - Leibniz
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