Re: Theorizing: chip select lines as clock speed selectors in a overclocked 6510 on a C64

From: silverdr_at_srebrnysen.com
Date: Thu, 23 Jun 2022 18:24:20 +0000
Message-Id: <427934AE-6EC6-4FA7-988A-26E296E33A33_at_srebrnysen.com>
> On 2022-06-22, at 13:48, tokafondo_at_tokafondo.name wrote:
> 
> [...]
> The clock divider would have its base clock at DOT clock, using the internal C64 clock circuit. That would ensure that when divided by eight it would be properly in sync with the rest of the chips of the system. It's just what the VIC-II does. I'll call that input ICLK.

I had once a discussion with Jens (yes, *that* Jens ;-) about relation between DOTCLOCK and "the rest of the chips of the system" and he claimed that using DOTCLOCK for basically anything, trusting it to be in sync with the rest is a no go... Although we haven't experienced any of the issues he said he had when trying to use DOTCLOCK, I have no reasons to distrust his words and take that we were simply lucky.

-- 
SD!
Received on 2022-06-23 21:00:02

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