> On 2022-05-04, at 13:28, Michal Pleban <lists_at_michau.name> wrote: > > Hello! > > What would happen if the 6510 got a /RESET signal while the RDY signal is low? At which bus cycle would it stop - before or after reading the reset vector from $FFFC? > > Question context: Suppose we have a C64 cartridge built on an FPGA. The FPGA needs some time to initialize. Before it does that, it could pull down the RDY signal so that the CPU doesn't start before the FPGA is ready. Modern FPGAs with built-in flash and Co. are narrowing the initialisation time gap on CPLDs significantly. Unless yours is known to be really slow on this, in the C64 context you may be able have a safe margin before the power-up cycle releases /RESET line[*]. I take this is important only on power-up as during warm RESET your FPGA is already loaded anyway. * - exception might be a broken reset circuit - something I found on one of my dev/testing boards during BeamRacer development. That caused a similar, although differently rooted problem. But yeah - the board was de facto broken, even if the failure did not get spotted earlier.Received on 2022-05-04 16:02:39
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