Re: 1571/1581 Sources: Macro WDTEST inserting NOP before reading WD177x status register / writing command register

On 3/24/22 22:33, Spiro Trikaliotis wrote:
> Hello Gerrit,
> 
> * On Thu, Mar 24, 2022 at 10:04:11PM +0100 Gerrit Heitsch wrote:
>> On 3/24/22 21:45, Spiro Trikaliotis wrote:
> 
>> The NOP only makes sense if there is something happening inside the 177x
>> that needs a bit of extra time to finish before the next access to whatever
>> register can happen.
> 
> There is, as I wrote in my first posting.
> 
> The 6502 absolute addressing is as follows (looking into the MOS 6502
> programming manual, appendix E.3):
> 
> Clock    Adress Bus      PC      DAta bus    comments
> Cycle
>    1        PC           PC + 1    OP CODE    fetch op code
>    2        PC + 1       PC + 2    ADL        fetch ADL
>    3        PC + 2       PC + 3    ADH        fetch ADH
>    4        ADH,ADL      PC + 3    Data       fetch Data
>    5        PC + 3       PC + 4    OP CODE    fetch new op code, execute old op cod
> 
> So, if I start an access to the WD177x status register at an PC with
> A0=A1=0, then A0=A1=1 will end in clock cycle 5. The CPU will try to
> force these values of A0 and A1.

Yes, but by that time the /CS-signal for the WDC will have been HIGH for 
quite some time so it won't feel bothered by what's on A0 und A1.

Looking at the timing diagram for the 6502, the address lines become 
valid while PHI1 is HIGH.


> So, I just accessed the WD177x at address $xxx0 (or ...4 or ...8 or
> ...C), and the values might be changed (even for a very short time) to
> $xxx3 (or ...7 or ... B or ...F - you get it).

No, you didn't access the WD177x since the upper address lines don't 
show the pattern where the WD is located and that will have forced /CS 
for the WD HIGH before PHI1 becomes LOW again.

  Gerrit