Re: Independent CPU/VIC-II setup

From: smf <smf_at_null.net>
Date: Wed, 2 Jun 2021 00:24:38 +0100
Message-ID: <1df34557-ae6a-1d8d-a14b-95dd846d2541_at_null.net>
By my rough calculation that slows the cpu down to 1mhz 42% of the time
& 0mhz 8% of the time (on reads and writes). While IIRC Supercpu has
full speed reads and a write fifo.

Ideally any new system would have VSP fix built in and I don't think
getting the VIC2 off the bus as quick as possible would add much complexity.

On 02/06/2021 00:09, Jim Brain wrote:

> Reading or writing to the VIC-II RAM does not require slowing down the
> CPU to 1MHz.  If the RAM is as fast as the CPU (50nS or so), then a
> RAM access within the VIC-II space can be executed at 20MHz speeds on
> the CPU side of the VIC-cycle, assuming the VIC is not in a
> badline/cycle stealing mode.  In fact, when it's not in such a mode,
> the CPU has 4-10 cycles to do as it pleases (assuming 8-20 MHz).  The
> only time slowdowns would occur is when the VIC is using both halves
> of the VIC cycle.
Received on 2021-06-02 02:00:41

Archive generated by hypermail 2.3.0.