Re: FPGA using Python language

From: silverdr_at_wfmh.org.pl
Date: Thu, 25 Feb 2021 11:50:55 +0100
Message-Id: <5C77F093-CDEA-44EA-AFD5-3B10ACEA5541_at_wfmh.org.pl>
> On 2021-02-24, at 23:58, smf <smf_at_null.net> wrote:
> 
> Well that is kinda like a cpu before it's got a program loaded into
> flash/ram/etc

I remember our nice discussion about ancient kings (in the quantity of one) and their vessels (in the same quantity). For you reimplementation of mask-fabricated chips using an FPGA was an "emulation" (in the sense of like with a "cpu running a program loaded into flash/ram/etc") and.. the same as back then I still don't agree with you on this one.

Yes, there has to be some working logic on there. At the very least the one needed to handle the actual gateware upload. But the blank FPGA in its core function is not more turing complete than a (very) large pile of, unconnected simple TTL chips. They can form a turing complete system once laid out and connected accordingly. But the mere fact that they exist on that huge pile doesn't make them a "cpu before it's got a program loaded into flash/ram/etc"

> (yes I understand the conceptual differences between the
> two, but it does not affect it's turing completeness).

It does to the huge pile (or even an ordered stack) of unconnected logic gates, doesn't it?

> An fpga is a
> thing before a bitstream is loaded, it's just not performing the logic
> calculations. There is no chip fab or 3d printer inside an fpga ready to
> lay out gates.

The same question I asked back then - Commodore used a programmable 82S100 for the original PLAs. Does that mean they used an "emulation of the real PLAs" that came later? Does that mean 82S100 based PLAs were cpus with turing complete ISA running a PLA program to emulate the real PLA and only the real, mask fabbed PLAs were not?

True, there is no chip fab or 3d printer inside an FPGA. But there is an equivalent of a hard-working dude running quickly around and connecting wires to all the required inputs and outputs of a huge number of TTL chips so that they can form complex, turing complete (or not) systems. Once the wires are removed (FPGA powered off) we're back to the huge pile of simple, unordered components.

-- 
SD! 
Received on 2021-02-25 12:00:02

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