Ok, but how did they manage to introduce an error in the IRQ triggering? I thought the transistor "map" was the same, just different process On Sun, Jan 3, 2021 at 9:32 PM Gerrit Heitsch <gerrit_at_laosinh.s.bawue.de> wrote: > > On 1/3/21 9:15 PM, Francesco Messineo wrote: > > Hi all, > > I always thought the old (6526 I guess) and the new (8521) CIAs were identical, > > then I've seen this code: > > > > testCIAVersion: > > //; Set NMI vector > > lda #<continue > > sta $fffa > > lda #>continue > > sta $fffb > > > > lda #$81 //;also don't forget to set mask. Setting $01 to an > > appropriate value will also help :-) (Bitbreaker/Oxyron) > > sta $dd0d > > > > //; Set timer to 5 cycles > > lda #4 > > sta $dd04 > > lda #0 > > sta $dd05 > > > > //; Clear the detection flag > > sta oldCIA > > > > //; Fire a 1-shot timer > > lda #%10011001 > > sta $dd0e > > > > //; This should be interrupted before the INC > > //; only if it's a newer chip. > > lda $dd0d > > lda $dd0d > > inc oldCIA > > > > jmp * //; just in case > > > > So it seems the NMI triggered by some CIA revisions has an off-by-one > > cycle error? > > Can anyone explain what's the difference between the two CIAs? > > > NMOS vs. HMOS-II process and die shrink. > > For a while the HMOS-II version was labeled '8521R0' before MOS went > back to the '6526' marking. You can tell by the datecode (end of '86 or > later = HMOS-II) and the '206A' or '216A' right of the datecode. > > Gerrit > >Received on 2021-01-03 22:02:34
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