16 bit data bus on a 6502.

I recently asked Bill Mensch during his VCF East talk about WDC releasing 16
bit data bus versions of its 6502 CPUs.

He basically answered: "If I were backed by Google or Microsoft, I would use
my technology to create CPUs that would outperform any other CPU in the
market". He also told about being able to create 6502 cores running at
several gigahertz -- with the money, of course.

I think that just a 16 bit data bus 65816 would be enough for many. There
are a lot of chips that allow direct addressing by a 16 bit data bus.

I once got a response from Bill Mensch himself:

Me: "Could I emulate a 16 bit data bus by sending the MSB of a 16 bit word
to the Parallel interface bus, that would be connected to the top eight pins
of the data bus of the display controller?

Or should I instead use some kind of buffer that would receive the LSB and
MSB portions, one after the another one, that would convert it to a 16 bit
word, and then send it to the display controller?"

Bill Mensch: "This is the approach I suggest, convert the two 8-bit values
to a 
16-bit word".

That would then require external circuitry to achieve that, and have the
6502 to make twice the work in every read or write operation. And surely
twice the code or at least make the code to work twice.

So... what about this?

Having two 65xx chips running in parallel, clocked by the same source,
connected every one of them to the same 16 bit data bus of a single RAM
chip. But one would go to the MSB and the other one to the LSB.

They would be running the very same software, stored in a ROM, or in a RAM
chip belonging to a different chip select line than the RAM chip they would
be sharing. The thing to resolve would be the addressing bus, but that could
be managed by the first chip, leaving the second not connected, just reading
or writing from its half data bus share.


What do you think?



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