On 31/08/2020 00:51, Jim Brain wrote: > >> // >> // GATE IN logic >> // >> reg r_w_latched; >> reg aec_latched; >> >> always _at_(gate_in_i, r_w_6502_i, aec_i) >> begin >> if (gate_in_i) >> begin >> r_w_latched = r_w_6502_i; >> aec_latched = aec_i; >> end >> end > Why the need to latch aec? And, in times when gate_in_i is low, what > should the values be? This is how it's implemented on the chip. I took this from the die shots and converted it straight forward to Verilog without much thinking. > >> // >> // Handle outputs >> // >> >> // Data bus to outside world is tristated during PHI1, PIO >> accesses and AEC being low >> wire data_7501_tristate = >> ~clock_i | >> ce_pio | >> ~aec_latched; >> >> assign r_w_7501_o = aec_latched ? r_w_latched : 1'bZ; > > Hmm, I have: > > assign r_w_7501 = (aec ? r_w_latched : 1) //(no latched aec) R/W# is definitely using the latched AEC! You can even see that the old metal trace with the AEC signal going to R/W# was disconnected at some place on the chip. > > Address is on bus for the entire cycle? (Also, for my understanding, > why ZZ instead of z? Is that a convention I need to learn?) Address drivers are still using the unmodified AEC signal. That means the 8501 behaves exactly as 6502/6510 here. Cheers, FrankReceived on 2020-08-31 10:00:03
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