Re: 7501/8501 R/W gate in

From: Jim Brain <brain_at_jbrain.com>
Date: Sun, 30 Aug 2020 22:15:35 -0500
Message-ID: <78e80abc-0f9f-db58-35a5-fcea442fe83e_at_jbrain.com>
On 8/30/2020 1:51 PM, Frank Wolf wrote:
> Just an additional note:
>
> The latched AEC is only used for the R/W# signal...
>
> The address and data but signals are using the unmodified AEC.
>
> But that's it. Finally. No other "magic".

This does not match the Verilog you posted.  aec_latched is used for 
more than just the r/w signal.

Data to the output bus, for example.

Jim
Received on 2020-08-31 06:00:04

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