Re: 7501/8501 R/W gate in

On 8/30/20 6:44 PM, Mario Kienspergher wrote:
> 
> 
> Am 30.08.20 um 18:04 schrieb Frank Wolf:
>> But GATE_IN is definitely a latch enable signal and R/W# is latched. I 
>> reversed it from the die
>> and my conclusions were tested and proven; you certainly followed my 
>> posts on F64 ;)
> 
> That's what I've figured out from the timing diagrams in the system 
> manual as well some time ago.
> 
>> On 30.08.2020 17:59, Gerrit Heitsch wrote:
>>> On 8/30/20 5:39 PM, Frank Wolf wrote:
>>>> Hi _at_ll,
>>>>
>>>> almost right... R/W# can change as long as GATE_IN is high. In other 
>>>> words: Francesco is right.
>>>
>>> Never saw it change anywhere else but on the rising edge of MUX 
>>> though. The difference between what you see on the scope and what the 
>>> circuit really does. :)
>>>
> 
> Of course you see it changing at the rising edge - that's when the latch 
> goes to transparent mode again. ;-)
> Even if the core changes R/W before (what it does IMHO) you won't see it 
> on the R/W pin outside because it's "masked" by the latch.

You can tie GateIN to HIGH and then see what the core really does. As I 
said, I have scope screenshots. You can see there when AEC tristates R/W 
and when TED takes over and drives R/W to HIGH. This is not visible when 
GateIN is connected to MUX.

  Gerrit