Re: Interesting JiffyDOS / C128 problem

From: Justin Cordesman <shadow_at_darksideresearch.com>
Date: Wed, 26 Aug 2020 05:51:58 -0700
Why not just rub the too slow PLA with cheetah blood?

Justin

> On Aug 26, 2020, at 05:49, Jeffrey Birt <birt_j_at_soigeneris.com> wrote:
> 
> Looking at the C128 manual and schematic I see the /OE for the ROMs comes directly from the PLA. I was not able to find a real data sheet for the 8721 so there is no timing diagram or other specs to refer to. I suppose this also means that variations between PLA versions might mean a faster part would work on one computer and not another.
> 
> From what Frank is saying I would guess that tGHQZ is the timing specification that is problematic.
> 
> I thought this might be a fun thing to look into, like the VIC Tower mod board. The person who originally contacted me about this issue was nice enough to mail the 'too fast' PROMs to me for some experimentation. I'm hoping one of my C128s will display the same symptoms.
> 
> Jeff Birt
> 
> -----Original Message-----
> From: Francesco Messineo <francesco.messineo@gmail.com> 
> Sent: Wednesday, August 26, 2020 2:14 AM
> To: cbm-hackers@musoftware.de
> Subject: Re: Interesting JiffyDOS / C128 problem
> 
>> On Wed, Aug 26, 2020 at 9:07 AM Baltissen, GJPAA (Ruud) <ruud.baltissen@apg.nl> wrote:
>> 
>> Jim Schreef:
>>> Never thought that buying slower ICs would fix issues,....
>> 
>> But why does it go wrong? AFAIK the 6502 reads the data at the end of the upper half of PHI2 and IMHO a faster ROM should not make any difference. Am I overlooking something?
> 
> 
> as I have already written in a previous answer in this thread, the likely problem is hold data time at the end of the cycle (falling phi2). 6502's datasheet indicates 10ns minimum hold time on a 1 MHz read cycle after phi2 falling edge. Some fast memories could have a shorter hold time.
> 
> 
> HTH
> Frank IZ8DWF
> 
> 
> 
> 
> 

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Why not just rub the too slow PLA with cheetah blood?<br>
<br>
Justin<br>
<br>
&gt; On Aug 26, 2020, at 05:49, Jeffrey Birt &lt;birt_j_at_soigeneris.com&gt; wrote:<br>
&gt; <br>
&gt; Looking at the C128 manual and schematic I see the /OE for the ROMs comes directly from the PLA. I was not able to find a real data sheet for the 8721 so there is no timing diagram or other specs to refer to. I suppose this also means that variations between PLA versions might mean a faster part would work on one computer and not another.<br>
&gt; <br>
&gt; From what Frank is saying I would guess that tGHQZ is the timing specification that is problematic.<br>
&gt; <br>
&gt; I thought this might be a fun thing to look into, like the VIC Tower mod board. The person who originally contacted me about this issue was nice enough to mail the 'too fast' PROMs to me for some experimentation. I'm hoping one of my C128s will display the same symptoms.<br>
&gt; <br>
&gt; Jeff Birt<br>
&gt; <br>
&gt; -----Original Message-----<br>
&gt; From: Francesco Messineo &lt;francesco.messineo@gmail.com&gt; <br>
&gt; Sent: Wednesday, August 26, 2020 2:14 AM<br>
&gt; To: cbm-hackers@musoftware.de<br>
&gt; Subject: Re: Interesting JiffyDOS / C128 problem<br>
&gt; <br>
&gt;&gt; On Wed, Aug 26, 2020 at 9:07 AM Baltissen, GJPAA (Ruud) &lt;ruud.baltissen@apg.nl&gt; wrote:<br>
&gt;&gt; <br>
&gt;&gt; Jim Schreef:<br>
&gt;&gt;&gt; Never thought that buying slower ICs would fix issues,....<br>
&gt;&gt; <br>
&gt;&gt; But why does it go wrong? AFAIK the 6502 reads the data at the end of the upper half of PHI2 and IMHO a faster ROM should not make any difference. Am I overlooking something?<br>
&gt; <br>
&gt; <br>
&gt; as I have already written in a previous answer in this thread, the likely problem is hold data time at the end of the cycle (falling phi2). 6502's datasheet indicates 10ns minimum hold time on a 1 MHz read cycle after phi2 falling edge. Some fast memories could have a shorter hold time.<br>
&gt; <br>
&gt; <br>
&gt; HTH<br>
&gt; Frank IZ8DWF<br>
&gt; <br>
&gt; <br>
&gt; <br>
&gt; <br>
&gt; <br>
</FONT>
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Received on 2020-08-26 15:02:03

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