> On 2020-08-08, at 01:34, tokafondo <tokafondo_at_gmail.com> wrote: > > Well... The VASYL communicates with the VIC-II at DOTCLOCK. No, not really. VASYL runs at DOTCLOCK speed but there is no way to "communicate with VIC" at that speed. > So the data that > the VIC-II requests is fed back by VASYL, instead of reaching the main RAM, > when using the extended command set, instead of the classic one. Is it that > way? Yes, although only when the programmable bitmap sequencer is enabled. Not when – as you call it – "using the extended command set". You can enable BeamRacer in the sense that all the new features become available but that does not automatically mean that the programmable sequencer is used. > So is then the DATA and ADDRESS bus running at DOTCLOCK also, between VIC-II > and VASYL? VIC does its accesses at PHI0 speed. The same happens when VIC registers are being written. You can feed data to VIC data lines faster than PHI0 but you can't make VIC latch the values faster. > I'm very insterested in how VASYL manages to isolate its own bus from the > rest of the system. There are controllable hardware buffers with tristate outputs between the buses. They are precisely signalled not to perform transmission to/from the main system buses when the isolation is required. Of course they need to be appropriately controlled also when the transmission is desirable. -- SD!Received on 2020-08-11 02:00:03
Archive generated by hypermail 2.3.0.