The timings of 8500 compared to 6510 are slightly different. 8500 (or 850x) are slightly faster. AEC has no influence on the RDY# line (or vice versa)... it just tri-states R/W#, D0-D7, A0-A15. In other words: If you want to control the data/Address bus you need to pull it too. /Frank On 13.06.2020 05:27, laubzega wrote: > Let me do some thread necromancy to ask about this very well known paragraph > from Gideon's freezer document: > > "It was attempted to pull –DMA low around 250 ns before the falling edge of > PHI2, so > after the R/–W line had stabilized. This works perfectly on a 6510, but > makes the 850x > CPU in a C64c crash. Apparently, this CPU does not like to see RDY ‘true’ on > a rising > edge of PHI2, and ‘false’ on the subsequent falling edge." > > > We have clocked hundreds of testing hours with BeamRacer running on several > 8500s. Not a single crash, despite stopping and restarting the CPU exactly > in this manner up to 200 times per frame. > > Has anyone actually experienced the issue described by Gideon? Could the > fact that we are pulling down just the RDY (as opposed to RDY and AEC he had > to manipulate jointly with the DMA line) have any significance? > > Thanks, > Milek > > > > > -- > Sent from: http://cbm-hackers.2304266.n4.nabble.com/ > >Received on 2020-06-13 10:00:02
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