Gentlemen, Another issue with that JED file is that there are no test vectors included in the file. That means there can be NO verification of proper output states after fusing. The Verification test may pass, but nothing is really tested. The output pins can not be tested by the PLA Programmer without test vectors. Any output pin may be dead and no one can tell after fusing. The first 'test' then is when the PLA is placed on the board and run operationally. If someone has a Truth Table of the 16 inputs vs the 8 outputs for all 48 Product Terms, the Test Vectors can be created. -- Sent from: http://cbm-hackers.2304266.n4.nabble.com/Received on 2020-05-30 01:49:13
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