Connecting a 8250 to a C64

From: Ruud Baltissen (Ruud.Baltissen_at_abp.nl)
Date: 2001-02-20 12:03:00

Hallo allemaal,

Here is the promised article. Warning: the part under the "Pin descriptions"
can look weird because I used tabs in the first place which didn't show up
in this mail. I added spaces to line everything but if the tabs still show
up in your email....

Connecting a 8250 or 16450 to a C64

The C64 is able to handle a RS232 communication thru the USERPORT but this
is limited to 1200 Baud. The book says 2400 is possible as well but it
stresses the system so much that parallel actions are almost impossible. A
solution is to connect an UART like the 6551. But the 6551 has its limits
and, AFAIK, has problems with the timing used by the 6510. Having easy
access to 8250s and 16450s and being familiar how to program them, I finally
choose for the 8250 and equivalents.

For simplifying things I only will mention the 8250 from now on.

<PRE>
          +---------------------+            16550
   D0    -+  1               40 +-   +5V
          |                     |    __
   D1    -+  2               39 +-   RI
          |                     |    ___
   D2    -+  3               38 +-   DCD
          |                     |    ___
   D3    -+  4               37 +-   DSR
          |                     |    ___
   D4    -+  5               36 +-   CTS
          |                     |
   D5    -+  6               35 +-   MR
          |                     |    ____
   D6    -+  7               34 +-   OUT1
          |                     |    ___
   D7    -+  8               33 +-   DTR
          |                     |    ___
  RCLK   -+  9               32 +-   RTS
          |                     |    ____
   SIN   -+ 10               31 +-   OUT2
          |        8250         |
  SOUT   -+ 11               30 +-   INTR
          |                     |            _____
   CS0   -+ 12               29 +-   NC      RXRDY
          |                     |
   CS1   -+ 13               28 +-   A0
   ___    |                     |
   CS2   -+ 14               27 +-   A1
_______   |                     |
BAUDOUT  -+ 15               26 +-   A2
          |                     |    ___
   XIN   -+ 16               25 +-   ADS
          |                     |            _____
  XOUT   -+ 17               24 +-   CSOUT   TXRDY
   __     |                     |
   WR    -+ 18               23 +-   DDIS
          |                     |
   WR    -+ 19               22 +-   RD
          |                     |    __
   GND   -+ 20               21 +-   RD
          +---------------------+

Pin descriptions

D0..D7         = databus
A0..2          = Addresslines
          ___
CS0, CS1, CS2  = ChipSlect-signals
    __
RD, RD         = active (H) OR active (L) signals read operation
    __
WR, WR         = active (H) OR active (L) signals read operation
MR             = Master Reset, active (H)
___
ADS            = positive edge latches A0..1 and CSx
INTR           = output, active (H) interrupt

RCLK           = Receiver ClocK, 16 * rate clock for receiver section
SIN            = Serial data Input
CTS            = input, Clear To Send
DSR            = input, Data Set Ready
DCD            = input,Data Carrier Detect
RI             = input,Ring Indicator
DTR            = output,Data Terminal Ready
RTS            = output,Request To Send
OUT1           = output
OUT2           = output
CSOUT          = output, active (H), indicates IC has been selected
DDIS           = output, active (L), indicates CPU is reading
BAUDOUT        = output, 16 * rate clock of transmitter section
SOUT           = Serial data OUTput
XIN            = clockinput
XOUT           = optional clockoutput
RXRDY / TXRDY  = receive / transmit FIFO is empty


D0..D7 have to be connected. to the databus.
A0..3 have to be connected to the corresponding addresslines.
CS0 and CS1 have to tied to +5V.

Personnally I don't like to use a whole I/O range for one IC so I normally
add an extra address decoder. I normally use a 74LS138 (3 to 8 multiplexer)
which enables me to decrease the range to just 8 bytes. The 138 has 6
inputs: A, B, C, /G1, /G2 and G. A, B and C determine which Y-output is
activated. The others are chipselect line. We connect G to A7. I/Ox is
connected to /G1. A6 to /G2. A3..5 is connected to C, B and A. Choose a
Y-output of your favour to be connected to /CS2.

CLK2 is not involved in generating the I/Ox signal for the simple reason
that all 65xx (-compatible) ICs have there own CLK2 input. The 8250 has _NO_
such equivalent. Its timing is controlled by the read- and write-signals.
INTEL (and ZILOG) IC have a read- AND write signal. Connecting R/W to RD and
/WR is not enough; the C= R/W signal is wider then the "data is valid"
range. Combining the R/W signal with CLK2 using a 74LS139 (2 to 4
multiplexer) does the trick. The /G input can be tied to GND.
RD and WR are not needed here and are tied to GND.

As CS0 and CS1 are not needed as well, we can tie them to +5V.

As all lines are stable, /ADS is tied to GND.

MR needs a positive pulse. As I remember well, I used the second half of the
139 as invertor to do the trick.

In 1987 I didn't need the INTR, but if needed by someone, a 7406 OC invertor
does the trick to connect INTR to /IRQ (or /NMI).

The above the is the computer side. Here is what to do with the
communication side.
I used a 1.8432 MHz crystal to feed XIN. XOUT not needed. The 8250/16450 can
go as high as 3.1 MHz, the 16550 up to 8 MHz. (1987, nowadays ???)
Connect BAUDOUT to RCLK.
Connect DTR, RTS and SOUT to the RS232 connector thru a 1488 or equivalent
(MAX232).
Connect RI, DCD, DSR, CTS and SIN to the RS232 connector thru a 1489 or
equivalent.
OUT1, OUT2, CSOUT and DDIS are not needed.


Connecting the 8250 to another C=.
IMHO the only difference is that you probably need some more decoding to do.
For the rest I don't see any other bear on the road.

Groetjes, Ruud

http://home.hccnet.nl/g.baltissen/index.htm


-
This message was sent through the cbm-hackers mailing list.
To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tml.hut.fi.

Archive generated by hypermail 2.1.1.