Hi! > - Bo > > > Hi, > > > > On your cbm page you state the CPU clock speed of the 7501/8501 machines > > (264/plus4 etc) is "variable". This explains all the different clock > > speed info when checking out the specs on the Net - but how come? Which > > 264/etc shipped at which clock speed, and why was this done? Any idea? > > > > (I have some CBM machines, btw, including a 2001, c128 and a plus4). The answer is simple: actually, _all "264 series machines" were shipped with the same clock characteristics. The clock is 'single clock' when the TED needs the bus for its screen related tasks or memory refresh, else 'twiee clock'. 'Single clock' is PHI0/20, while 'twiee clock' is PHI0/10 on a PAL machine (~= 886Khz and 1.7734Mhz; PHI0= 17.734472Mhz). For NTSC, PHI0 is 14.31818Mhz, and the divider is either 16 or 8 respectively. What you see, when programming a Plus/4 (or C-16 or C-116 or the rare 'prototypes') that the processor runs pretty fast when the TED screen refresh is at the border lines, while it gets halved when it is at the character ( or graphic) screen area. Best regards, L. - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail email@example.com.
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