Re: GO64 tech stuff?

From: Richard Atkinson (
Date: 2000-08-29 21:32:19

On Tue, 29 Aug 2000, Richard Atkinson wrote:

> I'm convinced TEST is changing the contents of the buffer, probably due to
> the BA AEC badline mechanism when 3 LSB of RASTER = YSCROLL. This buffer
> is almost certainly implemented as 12 40 bit long shift registers which
> are shifted during every cycle in the visible display area (assuming
> screen enabled). Thus it seems reasonable for the badline DMA mechanism to
> affect that cell and only that cell when a badline condition is given and
> then taken away in this manner. What I can't explain is why on line $044
> there are 3 characters replaced in the buffer, yet on line $45 only 1 but
> the screen loses only 7 vertical pixels on these two lines whereas it
> loses 8 on the later ones.

Worked it out. It is in fact entirely normal BA AEC badline behaviour. The
3 "idle" accesses occur at the end of the routine, when TEST is reset
again. It's just the normal 3 accesses that occur when YSCROLL = RASTER.
The cycle that resets TEST occurs on the first of the three accesses, and
since it is a write cycle it happens. During the next two cycles the
processor is halted but TEST is no longer low, so in fact the routine
doesn't halt the processor at all during TEST high, in contrast with the
other situations where it halts it for one cycle.

TEST only seems to increment RASTER every cycle; I can't see how it
affects any other standard functionality. This is *great*. I can't wait to
get my PAL C128s here so I can try out some 60Hz PAL routines. Mayhem in
Monsterland is begging to be converted :)


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